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A49FL004 4 mbit cmos 3.3volt-only firm ware hub/lpc flash memory preliminary preliminary (september, 2005, version 0.0) amic technology, corp. document title 4 mbit cmos 3.3 volt-only firmware hub/lpc flash memory revision history rev. no. history issue date remark 0.0 initial issue september 23, 2005 preliminary
A49FL004 4 mbit cmos 3.3volt-only firm ware hub/lpc flash memory preliminary preliminary (september, 2005, version 0.0) 1 amic technology, corp. features ? single power supply operation - low voltage range: 3.0 v - 3.6 v ? standard intel firmware hub/lpc interface - read compatible to intel? 82802 firmware hub devices - conforms to intel lpc interface specification revision 1.1 ? memory configuration - 512k x 8 (4 mbit) ? block architecture - uniform 4 kbytes sectors - uniform 64 kbyte overlay blocks - support full chip erase for address/address multiplexed (a/a mux) mode ? automatic erase and program operation - build-in automatic program ve rification fo r extended product endurance - typical 10 s/byte programming time - typical x s sector erase time - typical y s block erase time - typical z s chip erase time ? two configurable interfaces - in-system hardware interf ace: auto detection of firmware hub (fwh) or low pin count (lpc) interface for in-system read and write operations - address/address multiplexed (a/a mux) interface for programming on eprom programmers during manufacturing ? firmware hub (fwh)/low pin count (lpc) mode - 33 mhz synchronous operation with pci bus - 5-signal communication interface for in-system read and write operations - standard sdp command set - data polling and toggle bit features - block locking register for all blocks - register-based read and write protection for each block - 4 id pins for multiple chips selection - 5 gpi pins for general purpose input register - tbl pin for hardware write protection to boot block - wp pin for hardware write protection to whole memory array except boot block ? address/address multiplexed (a/a mux) mode - 11-pin multiplexed address and 8-pin data i/o interface - supports fast programming on eprom programmers - standard sdp command set - data polling and toggle bit features ? lower power consumption - typical 12ma active read current - typical 17ma program/erase current ? high product endurance - guarantee 100,000 program/erase cycles per single sector (preliminary) - minimum 20 years data retention ? compatible pin-out and packaging - 32-pin (8 mm x 14 mm) tsop - 32-pin plcc - optional lead-free (pb-free) package ? hardware data protection
A49FL004 preliminary (september, 2005, version 0.0) 2 amic technology, corp. general description the A49FL004 is a 4 mbit 3.0 volt-only flash memories used for bios storage in pcs and notebooks. this device is designed to use a single low voltage, ranging from 3.0 volt to 3.6 volt, power supply to perform in-system or off-system read, erase and program operati ons. the device conforms to intel? low pin count (lpc) interface specification revision 1.1 and also is compatible with intel 82802 firmware hub (fwh) for most pc and notebook applications. the A49FL004 supports two configurable interfaces: in-system hardware interface which can automatic detect the fwh or lpc memory cycle for in-system read and write operations, and address/address multiplexed (a/a mux) interface for fast manufacturing on eprom programmers. this device is designed to work with both intel family chipset and non-intel family chipset, it will provide pc and notebook manufacturers great flexibility and simplicity for design, procurement, and material inventory. the memory array of A49FL004 is divided into 128 uniform 4 kbyte sectors or 8 uniform 64 kbyte blocks (sector group - consists of sixteen adjacent se ctors). the sector or block erase feature in the A49FL004 a llows user to flexibly erase a memory area as 4kbyte or 64 kbyte by one single erase operation without affecting the data in others. the chip erase feature allows the whole memory to be erased in one single erase operation. the device can be programmed on a byte- by-byte basis after performing the erase operation. the program operation of a49f l004 is executed by issuing the program command code into command register. the internal control logic automat ically handles the programming voltage ramp-up and timing. the erase operation of the device is also executed by issuing the sector, block, or chip erase command code into command register. the internal control logic automatically h andles the erase voltage ramp- up and timing. the device offer data polling and toggle bit functions in fwh/lpc and a/a mux modes, the progress or completion of program and er ase operation can be detected by reading the data polling on i/o 7 or toggle bit on i/o 6 . the A49FL004 has a 64 kbyte top boot block. the boot block can be write protected by a hardware method controlled by the tbl pin or a register-based protection turned on/off by the block locking registers (fwh or lpc mode only). the rest of blo cks except boot block in the device also can be write protected by wp pin or block locking registers (fwh or lpc mode only). the A49FL004 is manufactured on amic ?s advanced nonvolatile technology. the devic e is offered in 32-pin tsop and plcc packages with optional environmental friendly lead-free package.
A49FL004 preliminary (september, 2005, version 0.0) 3 amic technology, corp. pin configurations figure 1: 32-pin plcc a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 21 22 23 24 25 26 27 28 29 12 13 11 8 9 5 7 6 i/o 7 we 32-pin plcc oe nc nc gnd ic 4 3 2 1 32 31 30 14 15 16 17 18 19 20 10 gpi1 gpi0 wp tbl id3 id2 id1 id0 fwh0 ic nc nc init lframe res res res res res nc gnd a/a mux lpc fwh ic nc nc init fwh4 res nc gnd nc lad0 gpi1 gpi0 wp tbl a/a mux lpc fwh fwh1 fwh2 gnd fwh3 res res res lad1 lad2 gnd lad3 res res res i/0 1 i/o 2 gnd i/o 3 i/o4 i/o 5 i/o 6 a/a mux lpc fwh a/a mux lpc fwh a8 a9 r s t nc r/c a10 gpi2 gpi3 r s t nc clk gpi4 gpi2 gpi3 r s t nc vdd clk gpi4 vdd vdd vdd vdd vdd figure 2: 32-pin tsop 32-lead tsop ( 8 mm x 14 mm ) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc gnd ic a10 r/c vd d rst a9 a8 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 i/o 0 i/o 2 vss i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 vdd we oe vd d nc a/a mux lpc fwh nc nc gnd ic gpi4 clk vd d rst gpi3 gpi2 gpi1 gpi0 wp tbl vd d nc nc nc gnd ic gpi4 clk vd d rst gpi3 gpi2 gpi1 gpi0 wp tbl vd d nc a/a mux lpc fwh i/o 1 a0 a1 a2 a3 res init lframe n c lad3 lad2 gnd lad1 lad0 res res res res res res res res init lframe nc lad3 lad2 gnd lad1 lad0 res res res res res res res
A49FL004 preliminary (september, 2005, version 0.0) 4 amic technology, corp. figure 3: block diagram fwh/lpc mode interface fwh[3:0] or lad[3:0] fwh4 or lframe clk gpi[4:0] a/a mode interface a[10:0] i/o[7:0] we oe r/c ic rst tbl wp init erase/program voltage generator high voltage switch address latch x-decoder y-decoder control logic i/o buffers y - gating memory array data latch sense amp
A49FL004 preliminary (september, 2005, version 0.0) 5 amic technology, corp. table 1: pin description notes: in=input, i/o=input/output. interface descriptions symbol type a/a fwh lpc a[10:0] in x addresses inputs: for inputting the multiplex address in a/a mux mode. row and column address are latched during a read or write cycle controlled by c r/ pin. i/o[7:0] i/o x data inputs/outputs: used for a/a mux mode only, to input command/data during write operation and to output data during read operation. the data pins float to tri-state when oe is high. oe in x output enable: control the device?s output buffers during a read cycle. oe is a active low. we in x write enable: active the device for write operation. we is active low. ic in x x x interface configuration select: this pin determines which mode is selected. when pulls high, the device enters into a/a mux mode. when pulls low, fwh/lpc mode is selected. this pin must be setup during power-up or system reset, and stays no change during operation. this pin is internally pulled down with a resistor between 20-100 k ?. init in x x initialize: this is the second reset pin for in-system use. init and rst pin are internally combined and initialize a device reset when driven low. id[3:0] in x these four pins are part of the mechanis m that allows multiple fwh devices to be attached to the same bus. the strapping of these pins is used to identify the component. the boot device must have id[3:0]=0000b and it is recommended that all subsequent devices should us e sequential up-count strapping. these pins are internally pulled-down with a resistor between 20-100 k ?. gpi[4:0] in x x fwh/lpc general purpose inputs: used to set the gpi_reg for system design purpose only. the value of gpi_reg can be read through fwh interface. the state of these pins can be read immediat ely at boot, through fwh/lpc internal registers. these pins should be set at desired state before t he start of the pci clock cycle for read operation and should re main on change until the end of the read cycle. unused gpi pins must not be floated. tbl in x x top block lock: when pulls low, it enables the hardware write protection the state for top boot block. when pulls high, it disables the hardware write protection. fwh[3:0] i/o x fwh address and data: the major i/o pins for transmitting data, address and command code in fwh mode. clk in x x fwh/lpc clock: to provide a synchronous clock for fwh and lpc mode operations. fwh4 in x fwh input: to indicate the start of a fwh memory cycle operation. also used to abort a fwh memory cycle in progress. rst in x x x reset: to reset the operation of the device and return to standby mode. wp in x x write protect: when pulls low, it enables the hardware write protection to the memory array except the top boot block. when pulls high, it disables hardware write protection except the top boot block. c r/ in row/column select: to indicate to the row or column address in a/a mux mode. when this pin goes low, the row address is latched. when this pin goes high, the column address is latched. lad[3:0] i/o x lpc address and data: the major i/o pins for transmitting data, addresses and command code in lpc mode. lframe in x lpc frame: to indicate the start of a lpc memory cycle operation. also used to abort a lpc memory cycle in progress. res x x reserved. reserved function pins for future use. vdd x x x device power supply. vss x x x ground. nc x x x no connection.
A49FL004 preliminary (september, 2005, version 0.0) 6 amic technology, corp. fwh mode selection the A49FL004 can operate in two configurable interfaces: the in-system hardware interface and address/address multiplexed (a/a mux) interface controlled by ic pin. if the ic pin is set to logic high (v ih ), the devices enter into a/a mux interface mode. if the ic pin is set logic low (v il ), the device will be in in-system hardware interface mode. during the in- system hardware interface mode, the device can automatically detect the firmware hub (fwh) or low pin count (lpc) memory cycle sent from host system and response to the command accordingly. the ic pin must be setup during power-up or system reset, and stays no change during device operation. when working in-system, typically on a pc or notebook for intel platform, the A49FL004 enters into the fwh mode automatically. the device is configured to interface with its host using intel?s firmware hub proprietary protocol. communication between the host (intel ich) and the A49FL004 occurs via the 4-bit i/o communication signal, fwh[3:0] and fwh4. in a/a mux mode, the device is programmed via 11-bit address a[10:0] and 8-pin data i/o[7:0] interfaces. the address inputs are multiplexed in row and column selected by column the control signal c r/ . the column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. fwh mode operation in fwh mode, the A49FL004 is connected through a 5-pin communication interface - fwh[3:0] and fwh4 pins to work with intel? family of i/o controller hubs (ich) chipset platforms. the fwh mode also supports jedec standard software data protection (sdp) product id entry, byte program, sector erase, and block erase command sequences. the chip erase command sequence is only available in a/a mux mode. the addresses and data are transmitted through the 4-bit fwh[3:0] bus synchronized with the input clock on clk pin during a fwh memory cycle operation. the address or data on fwh[3:0] bus is latched on the rising edge of the clock. the device enters standby mode when fwh4 is high and no internal operation is in progress. the device is in ready mode when fwh4 is low and no activity is on the bus. fwh read operation fwh read operations read from the memory cells or specific registers in the fwh device. a valid fwh read operation starts when fwh4 is low as clk rises and a start value ?1101b? is on fwh[3:0]. addresses and data are transferred to and from the device decided by a series of ?fields?. field sequences and contents are strictly defined for fwh read operations. refer to table 2 for fwh read cycle definition. fwh write operation fwh write operations write the fwh interface or fwh registers. a valid fwh write operation starts when fwh4 is low as clk rises and a start value ?1110b? is on fwh[3:0]. addresses and data are transferred to and from the device decided by a series of ?fields?. field sequences and contents are strictly defined for fwh write operations. refer to table 3 for fwh write cycle definition. fwh abort operation the fwh4 signal indicates the start of a memory cycle or the termination of a cycle in fwh mode. asserting fwh4 for one or more clock cycle with a valid start value on fwh[3:0] will initiate a memory read or memory write cycle. if the fwh4 is driven low again for one or more clock cycles during this cycle, this cycle will be terminated and the device will wait for the abort command ?1111b? to release the fwh[3:0] bus. if the abort occurs during the program or erase operation such as checking the operation status with data polling (i/o 7 ) or toggle bit (i/o 6 ) pins, the read status cycle will be aborted but the internal program or erase operation will not be affected. only the reset operation initiated by rst or init pin can terminate the program or erase operation. response to invalid fields during fwh operations, the device will not explicitly indicate that it has received invalid field sequences. the response to specific invalid fields or sequences is as follows: address out range: the fwh address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by A49FL004. address a22 has the special function of directing reads and writes to the flash memory (a22=1) or to the register space (a22=0). invalid imsize field: if the fwh device receives and invalid size field during a read or write operation, the device will reset and no operation will be attempted. the A49FL004 will not generate any kind of response in this situation. invalid size field for a read/write cycles are anything but ?0000b?.
A49FL004 preliminary (september, 2005, version 0.0) 7 amic technology, corp. table 2: fwh read cycle figure 4: fwh memory read cycle waveforms clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 start idsel imaddr imsize tar0 tar1 rsync data tar0 tar1 fwh4 fwh[3:0] clock cycle field fwh[3:0] direction descriptions 1 start 1101 in start of cycle: ?1101b? to indicate the start of a memory read cycle. fwh4 must be active (low) for the part to respond. only the last start field (before fwh4 transition high) should be recognized. the start field contents indicate and fwh read cycle. 2 idsel 0000 to 1111 in id select cycle: indicates which fwh device should respond. if the idsel field matches the value set on id[3:0] pins, then the particular fwh device will respond to subsequent commands. 3-9 imaddr yyyy in address cycle: this is the 28-bit memory address. the addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a27-24 on fwh[3:0] first, and a3-a0 on fwh[3:0] last). 10 imsize 0000 in memory size cycle: indicates how many bytes will be or transferred during multi-byte operations. the A49FL004 only support ?0000b? for one byte operation. 11 tar0 1111 in then float turn-around cycle 0: the master (intel ich) has driven the bus to all?1?s and then float the bus. 12 tar1 1111 (float) float then out turn-around cycle 1: the device takes control of the bus during this cycle. 13 rsync 0000 (ready) out ready sync: the fwh device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14-15 data yyyy out data cycles: the 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., i/o 3 ? i/o 0 on fwh[3:0] first, then i/o 7 ? i/o 4 on fwh[3:0] last). 16 tar0 1111 out then float turn-around cycle 0: the fwh device has driven the bus to all ?1?s and then float the bus. 17 tar1 1111 (float) float then in turn-around cycle 1: the master (intel ich) resumes control of the bus during this cycle.
A49FL004 preliminary (september, 2005, version 0.0) 8 amic technology, corp. table 3: fwh write cycle figure 5: fwh write waveforms clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 start idsel imaddr imsize tar0 tar1 rsync data tar0 tar1 fwh4 fwh[3:0] clock cycle field fwh[3:0] direction descriptions 1 start 1101 in start of cycle: ?1101b? to indicate the start of a memory write cycle. fwh4 must be active (low) for the part to respond. only the last start field (before fwh4 transitioning high) should be recognized. the start field contents indicate an fwh write cycle. 2 idsel 0000 to 1111 in id select cycle: indicates which fwh device should respond. if the idsel field matches the value set on id[3:0] pins, then the particular fwh device will respond to subsequent commands. 3-9 imaddr yyyy in address cycle: this is the 28-bit memory address. the addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a27-24 on fwh[3:0] first, and a3-a0 on fwh[3:0] last). 10 imsize 0000 in memory size cycle: indicates how many bytes will be or transferred during multi-byte operations. the A49FL004 only supports ?0000b? for one byte operation. 11-12 data yyyy in data cycles: the 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., i/o 3 ? i/o 0 on fwh[3:0] first, then i/o 7 ? i/o 4 on fwh[3:0] last). 13 tar0 1111 in then float turn-around cycle 0: the master (intel ich) has driven the bus to all?1?s and then float the bus. 14 tar1 1111 (float) float then out turn-around cycle 1: the device takes control of the bus during this cycle. 15 rsync 0000 (ready) out ready sync: the fwh device indicates that it has received the data or command. 16 tar0 1111 out then float turn-around cycle 0: the fwh device has driven the bus to all ?1?s and then float the bus. 17 tar1 1111 (float) float then in turn-around cycle 1: the master (intel ich) resumes control of the bus during this cycle.
A49FL004 preliminary (september, 2005, version 0.0) 9 amic technology, corp. lpc mode selection the A49FL004 can operate in two configurable interfaces: the in-system hardware interface and address/address multiplexed (a/a mux) interface controlled by ic pin. if the ic pin is set to logic high (v ih ), the devices enter into a/a mux interface mode. if the ic pin is set logic low (v il ), the devices will be in in-system hardware interface mode. during the in- system hardware interface mode, the devices can automatically detect the firmware hub (fwh) or low pin count (lpc) memory cycle sent from host system and response to the command accordingly. the ic pin must be setup during power-up or system reset, and stays no change during device operation. when working in-system, typically on a pc or notebook for non intel platform, the A49FL004 is connected to the host system through a 5-pin communication interface operated based on a 33-mhz synchronous clock. the 5-pin interface is defined as lad[3:0] and lframe pins under lpc mode for easy understanding as to those existing compatible products. when working off-system, typically on a eprom programmer, the device is operated through 11-pin multiplexed address - a[10:0] and 8-pin data i/o - i/o[7:0] interfaces. the memory addresses of device are input through two bus cycles as row and column addresses controlled by a c r/ pin. lpc mode operation in lpc mode, the A49FL004 is connected through a 5-pin communication interface - lad[3:0] and lframe pins to work with non intel? family of south bridge chipset platforms. the lpc mode also supports jedec standard software data protection (sdp) product id entry, byte program, sector erase, and block erase command sequences. the chip erase command sequence is only available in a/a mux mode. the addresses and data are transmitted through the 4-bit lad[3:0] bus synchronized with the input clock on clk pin during a lad memory cycle operation. the address or data on lad[3:0] bus is latched on the rising edge of the clock. the pulse of lframe pin is inserted for one clock indicates the start of a lpc memory read or memory write cycle. the address or data on lad[3:0] is latched on the rising edge of clk. the device enters standby mode when lframe is high and no internal operation is in progress. the device is in ready mode when lframe is low and no activity is on the lpc bus. lpc mode memory read/write operation in lpc mode, the A49FL004 uses the 5-pin lpc interface includes 4-bit lad[3:0] and lframe pins to communicate with the host system. the addresses and data are transmitted through the 4-bit lad[3:0] bus synchronized with the input clock on clk pin during a lpc memory cycle operation. the address or data on lad[3:0] bus is latched on the rising edge of the clock. the pulse of lframe signal inserted for one or more clocks indicates the start of a lpc memory read or write cycle. once the lpc memory cycle is started, asserted by lframe , a start value ?0000b? is expected by the device as a valid command cycle. then a cyctype + dir value (?010xb? for memory read cycle or ?011xb? for memory write cycle) is used to indicates the type of memory cycle. refer to table 4 and 5 for lpc memory read and write cycle definition. there are 8 clock fields in a lpc memory cycle that gives a 32 bit memory address a31 - a0 through lad[3:0] with the most-significant nibble first. the memory space of A49FL004 is mapped directly to top of 4 gbyte system memory space. see figure 8 for system memory map. the A49FL004 is mapped to the address location of (ffffffffh - fff80000h), the a31- a19 must be loaded with ?1? to select and activate the device during a lpc memory operation. only a18 - a0 is used to decode and access the 512 kbyte memory. lpc abort operation the lframe is driven low for one or more clock cycles during a lpc cycle, the cycle will be terminated and the device will wait for the abort command. the host may drive the lad[3:0] with ?1111b? (abort command) to return the device to the ready mode. if abort occurs during a write operation such as checking the operation status with data polling (i/o 7 ) or toggle bit (i/o 6 ) pins, the read status cycle will be aborted but the internal program or erase operation will not be affected. in this case, only the reset operation initiated by rst or init pin can terminate the write operation. response to invalid fields during lpc operations, the A49FL004 will not explicitly indicate that it has received invalid field sequences. the responses to specific invalid fields or sequence is as follows: address out of range: the A49FL004 will only response to address range as specified in table 9. address a22 has the special function of directing reads and writes to the flash memory (a22=1) or to the register space (a22=0). id mismatch: the A49FL004 will compare id bits in the address field with the hardware strapping. if there is a mismatch, the device will ignore the cycle.
A49FL004 preliminary (september, 2005, version 0.0) 10 amic technology, corp. table 4: lpc memory read cycle definition figure 6: lpc single-byte read waveforms lclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 start address tar0 tar1 sync data tar0 tar1 lframe lad[3:0] cyctype + dir clock cycle field lad[3:0] direction descriptions 1 start 0000 in start of cycle: ?0000b? indicates the start of a lpc memory cycle. lframe must be active low (low) for the part to respond. only the last field latched before lframe transitions high will be recognized. 2 cyctype + dir 010x in cycle type: indicates the type of a lpc memory read cycle. cyctype: bits 3-2 must be ?01b? for memory cycle. dir: bit 1 = ?0b? indicates the type of cycle for read. bit 0 is reserved. 3-10 addr yyyy in address cycles: this is the 32-bit memory address. the addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a31-28 on lad[3:0] first, and a3-a0 on lad[3:0] last). 11 tar0 1111 in then float turn-around cycle 0: the host has driven the bus to all?1?s and then float the bus. 12 tar1 1111 (float) float then out turn-around cycle 1: the A49FL004 takes control of the bus during this cycle. 13 sync 0000 out sync: the device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14-15 data 1111 out data cycles: the 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., i/o 3 ? i/o 0 on lad[3:0] first, then i/o 7 ? i/o 4 on lad[3:0] last). 16 tar0 1111 in then float turn-around cycle 0: the host has driven the bus to all ?1?s and then float the bus. 17 tar1 1111 (float) float then out turn-around cycle 1: the A49FL004 resumes control of the bus during this cycle.
A49FL004 preliminary (september, 2005, version 0.0) 11 amic technology, corp. table 5: lpc memory write cycle definition figure 7: lpc write waveforms lclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 start address tar0 tar1 sync data tar0 tar1 lframe lad[3:0] cyctype + dir clock cycle field lad[3:0] direction descriptions 1 start 0000 in start of cycle: ?0000b? to indicate the start of a lpc memory cycle. lframe must be active low (low) for the part to respond. only the last field latched before lframe transitions high will be recognized. 2 cyctype + dir 011x in cycle type: indicates the type of a lpc memory write cycle. cyctype: bits 3-2 must be ?01b? for memory cycle. dir: bit 1 = ?1b? indicates the type of cycle for write. bit 0 is reserved. 3-10 addr yyyy in address cycles: this is the 32-bit memory address. the addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a31-28 on lad[3:0] first, and a3-a0 on lad[3:0] last). 11-12 data yyyy in data cycles: the 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., i/o 3 ? i/o 0 on lad[3:0] first, then i/o 7 ? i/o 4 on lad[3:0] last). 13 tar0 1111 in then float turn-around cycle 0: the host has driven the bus to all?1?s and then float the bus. 14 tar1 1111 (float) float then out turn-around cycle 1: the A49FL004 takes control of the bus during this cycle. 15 sync 0000 out sync: the device indicates the least-significant nibble of data byte will be ready in next clock cycle. 16 tar0 1111 out then float turn-around cycle 0: the A49FL004 has driven the bus to all ?1?s and then float the bus. 17 tar1 1111 (float) float then in turn-around cycle 1: the host resumes control of the bus during this cycle.
A49FL004 preliminary (september, 2005, version 0.0) 12 amic technology, corp. multiple device selection multiple A49FL004 devices may be strapped to increase memory densities in a system. the four id pins, id[3:0], allow up to 16 devices to be attached to the same bus by using different id strapping in a system, bios support, bus loading, or the attaching bridge may limit this number. the boot device must have an id of ?0000b? (determined by id[3:0]); subsequent devices use incremental numbering, equal density must be used with multiple devices. multiple device selection for firmware hub memory cycle for firmware memory re ad/write cycles, hardware strapping values on id[3:0] must match the values in idsel field. see table x for multiple device selection configurations. the a 49fl004 will compare the idsel field with id[3:0] ?s strapping values. if there is a mismatch, the device will ignore the reminder of the cycle. table 6: fwh multiple device selection configuration device # id[3:0] idsel 0 (boot device) 0000 0000 1 0001 0001 2 0010 0010 3 0011 0011 4 0100 0100 5 0101 0101 6 0110 0110 7 0111 0111 8 1000 1000 9 1001 1001 10 1010 1010 11 1011 1011 12 1100 1100 13 1101 1101 14 1110 1110 15 1111 1111 multiple device selection for lpc memory cycle for lpc memory read/write cycles, id information is included in the address bits of every cycle. the id bits in the address field are the reverse of the hardware strapping. see tabl e x2 for multiple device selection configurations. the A49FL004 will compare these bits with id[3:0]?s strapping values. if there is a mismatch, the device will igno re the remainder of the cycle. table 7: lpc multiple device selection configuration device # id[3:0] address range 0 (boot device) 0000 1111 1 0001 1110 2 0010 1101 3 0011 1100 4 0100 1011 5 0101 1010 6 0110 1001 7 0111 1000 8 1000 0111 9 1001 0110 10 1010 0101 11 1011 0100 12 1100 0011 13 1101 0010 14 1110 0001 15 1111 0000
A49FL004 preliminary (september, 2005, version 0.0) 13 amic technology, corp. register the A49FL004 has two registers include the general purpose inputs register (gpi_reg) and block locking register (bl_reg). both registers are available in fwh and lpc mode only. the gpi_reg can be read at ffbc0100h in the 4 gbyte system memory map. the bl_reg can be read through ffbx0002h where x=f-0h. refer to table 9 for bl_reg. general purpose inputs register the A49FL004 contains and 8-bit general purpose inputs register (gpi_reg) available in fwh and lpc modes. only bit 4 to bit 0 are used in the current version, and bit 7 to bit 5 are reserved for the future use. the gpi_reg is a pass-through register with the value set by gpi[4:0] pin during power-up. the gpi_reg is used for the system design purpose only, the device does not use this register. this register is read only and can be read at address location ffbc0100h in the 4 gbyte system memory map through a memory read cycle. refer to table 8 for general purpose input register definition. table 8: general purpose inputs register block locking registers the A49FL004 supports block read-lock, write-lock, and lockdown features through a set of block locking registers. each memory block has an associated 8-bit read/writable block locking register. only bit 2 to bit 0 are used in current version and bit 7 to bit 3 are reserved for future use. the default value of bl_reg is ?01h? at power up. the definition of bl_reg is listed in table 8. the fwh/lpc register configuration map of A49FL004 is shown in table 9. unused register will be read as 00h table 9: A49FL004 block locking register address pin number bit bit name function 32-plcc 32-tsop 7:5 - reserved - - 4 gpi[4] gpi_reg bit 4 30 6 3 gpi[3] gpi_reg bit 3 3 11 2 gpi[2] gpi_reg bit 2 4 12 1 gpi[1] gpi_reg bit 1 5 13 0 gpi[0] gpi_reg bit 0 6 14 memory address mnemonic register name protected block address range ffbf0002h t_block_lk top block lock register (block 64) 70000h ? 7ffffh ffbe0002h t_minus01_lk top block [-1] lo ck register (block 64) 60000h ? 6ffffh ffbd0002h t_minus02_lk top block [-2] lo ck register (block 64) 50000h ? 5ffffh ffbc0002h t_minus03_lk top block [-3] lo ck register (block 64) 40000h ? 4ffffh ffbb0002h t_minus04_lk top block [-4] lo ck register (block 64) 30000h ? 3ffffh ffba0002h t_minus05_lk top block [-5] lo ck register (block 64) 20000h ? 2ffffh ffb90002h t_minus06_lk top block [-6] lo ck register (block 64) 10000h ? 1ffffh ffb80002h t_minus07_lk top block [-7] lo ck register (block 64) 00000h ? 0ffffh
A49FL004 preliminary (september, 2005, version 0.0) 14 amic technology, corp. table 10: block lock register bit definition data reserved bit 7:3 read-lock bit 2 lock-down bit 1 write-lock bit 0 function 00h 00000 0 0 0 full access. 01h 00000 0 0 1 write locked. default state at power-up. 02h 00000 0 1 0 locked open (full access locked down). 03h 00000 0 1 1 write-locked down. 04h 00000 1 0 0 read locked. 05h 00000 1 0 1 read and write locked. 06h 00000 1 1 0 read-locked down 07h 00000 1 1 1 read-locked and write-locked down data function 7:3 reserved 2 read-lock 1 = prevents read operations in the block where set 0 = normal operation for reads in the block where clear. this is the default state. 1 lock-down 1 = prevents further set or clear operations to the write-lock and read-lock bits. lock-down only can be set but not clear. the block will remain lock-down until reset (with rst or init ), or until the device is power-on reset. 0 = normal operation for write-lock and read-lock bit altering in the block where clear. this is the default state. 0 write-lock 1 = prevents program or erase operations in t he block where set. this is the default state. 0 = normal operation for programming and erase in the block where clear.
A49FL004 preliminary (september, 2005, version 0.0) 15 amic technology, corp. address/address multiplexed (a/a mux) mode read/write operation the A49FL004 offers a address/address multiplexed (a/a mux) mode for off-system operation, typically on an eprom programmer, similar to a traditional flash memory except the address input is multiplexed. in the a/a mux mode, the programmer must drive the oe pin to low (v il ) for read or we pins to low for write operation. the devices have no chip enable ( ce ) pin for chip selection and activation as traditional flash memory. the c r/ , oe and we pins are used to activate the device and control the power. the 11 multiplex address pins - a[10:0] and a c r/ pin are used to load the row and column addresses for the target memory location. the row addresses (internal address a10 - a0) are latched on the falling edge of c r/ pin. the column addresses (internal address a21 - a11) are latched on the rising edge of c r/ pin. the A49FL004 use a18 - a0 respectively. during a read operation, the oe signal is used to control the output of data to the 8 i/o pins - i/o[7:0]. during a write operation, the we signal is used to latch the input data from i/o[7:0]. see table 11 for bus operation modes. table 11: a/a mux mode operation selection notes: 1. x can be v il or v ih . 2. refer to table 12 for the manufacturer id and device id of devices. the A49FL004 provides three levels of data protection for the critical bios code of pc and notebook. it includes memory hardware write protection, hardware data protection and software data protection. sector-erase operation the A49FL004 contains 128 uniform 4 kbyte sectors. a sector erase command is used to erase an individual sector. see table 11 for sector/block address table. in fwh/lpc mode, an erase operation is activated by writing the six-byte command sequence through six consecutive write memory cycles with sector erase command (30h), and sector address (sa) in the last bus cycle. in a/a mux mode, an erase operation is activated by writing the six-byte command in six consecutive bus cycles. pre- programs the sector is not required prior to an erase operation. block-erase operation the A49FL004 c ontains eight uniform 64 kbyte blocks. a block erase command is used to erase an individual block. see table 13 for sector/block address table. in fwh/lpc mode, an erase operation is activated by writing the six-byte command sequence through six consecutive write memory cycles with block erase command (50h), and block address (ba) in the last bus cycle. in a/a mux mode, an erase operation is activated by writing the six-byte command in six consecutive bus cycles. pre- programs the block is not requir ed prior to an erase operation. chip-erase the entire memory array can be erased by chip erase operation available under the a/a mux mode operated by eprom programmer only. pre-programs the device is not required prior to the chip erase operation. chip erase starts immediately after a six-bus-cycle chip erase command sequence. all commands will be ignored once the chip erase operation has started. the data polling on i/o 7 or toggle bit on i/o 6 can be used to detect the progress or completion of erase operation. the device will return back to standby mode after the completion of the chip erase. write operation status detection in program operation, the data is programmed into the devices (to a logical ?0?) on a byte-by-byte basis. in fwh and lpc mode, a program operation is activated by writing the three-byte command sequence and program address/data mode rst oe we address i/o read v ih v il v ih x (1) d out write v ih v ih v il x d in standby v ih v ih v ih x high z output disable v ih v ih x x high z reset v il x x x high z a2 ? a21 = x, a1 = v il , a0 = v il , and a1 = v ih , a0 = v ih manufacturer id (2) product identification v ih v il v ih a2 ? a21= x, a1 = v il , a0 = v ih device id
A49FL004 preliminary (september, 2005, version 0.0) 16 amic technology, corp. through four consecutive memory write cycles. in a/a mux mode, a program operation is activated by writing the three- byte command sequence and program address/data through four consecutive bus cycles. the row address (a10 - a0) is latched on the falling edge of c r/ and the column address (a21 - a11) is latched on the rising edge of c r/ . the data is latched on the rising edge of we . once the program operation is started, the internal control logic automatically handles the internal programming voltages and timing. a data ?0? can not be programmed back to a ?1?. only erase operation can convert ?0?s to ?1?s. the data polling on i/o 7 or toggle bit on i/o 6 can be used to detect when the programming operation is completed in fwh, lpc, and a/a mux modes. data polling (i/o 7 ) the device provides a data polling feature to indicate the progress or the completion of a program or erase operation in all modes. during a program operation, an attempt to read the device will result in the complement of the last loaded data on i/o 7 . once the program cycle is complete, the true data of the last loaded data is valid on all outputs. during an erase operation, an attempt to read the device will result a ?0? on i/o 7 . after the erase cycle is complete, an attempt to read the device will result a ?1? on i/o 7 . toggle bit (i/o 6 ) the A49FL004 also provides a toggle bit feature to detect the progress or the completion of a program or erase operation. during a program or erase operation, an attempt to read data from the devices will result in i/o 6 toggling between ?1? and ?0?. when the program or erase operation is complete, i/o 6 will stop toggling and valid data will be read. toggle bit may be accessed at any time during a program or erase operation. data protection the device features a software data protection function to protect the device from an unintentional erase or program operation. it is performed by jedec standard software data protection (sdp) command sequences. see table 14 for sdp command definition. a program operation is initiated by three memory write cycles of unlock command sequence. a chip (only available in a/a mux mode), sector or block erase operation is initiated by six memory write cycles of unlock command sequence. during sdp command sequence, any invalid command or sequence will abort the operation and force the device back to standby mode. memory hardware write protection the A49FL004 has a 64 kbyte top boot block. when working in-system, the memory hardware write protection feature can be activated by two control pins - top block lock ( tbl ) and write protection ( wp ) for both fwh and lpc modes. when tbl is pulled low (v il ), the boot block is hardware write protected. a sector erase, block erase, or byte program command attempts to erase or program the boot block will be ignored. when wp is pulled low (v il ), the block 0 ~ block 6 of A49FL004 (except the boot block) are hardware write protected. any attempt to erase or program a sector or block within this area will be ignored. both tbl and wp pins must be set low (v il ) for protection or high (v ih ) for un-protection prior to a program or erase operation. a logic level change on tbl or wp pin during a program or erase operation may cause unpredictable results. the tbl and wp pins work in combination with the block locking registers. when active, these pins write protect the appropriate blocks regardless of the associated block locking registers setting. hardware data protection hardware data protection protects the devices from unintentional erase or program operation. it is performed by the device automatically in the following three ways: (a) v dd detection: if v dd is below 1.8 v (typical), the program and erase functions are inhibited. (b) write inhibit mode: holding any of the signal oe low, or we high inhibits a write cycle (a/a mux mode only). (c) noise/glitch protection: pulses of less than 5 ns (typical) on the we input will not initiate a write cycle (a/a mux mode only). reset any read, program, or erase operation to the devices can be reset by the init or rst pins. init and rst pins are internally hard-wired and have same function to the devices. the init pin is only available in fwh and lpc modes. the rst pin is available in all modes. it is required to drive init or rst pins low during system reset to ensure proper initialization. during a memory read operation, pulls low the init or rst pin will reset the devices back to standby mode and then the fwh[3:0] of fwh interface or the lad[3:0] of lpc interface will go to high impedance state. during a program or erase operation, pulls low the init or rst pin will abort the program or erase operation and reset the devices back to standby mode. a reset latency will occur before the devices resume to standby mode when such reset is performed. when a program or erase operation is reset before the completion of such operation, the memory contents of devices may become invalid due to an incomplete program or erase operation. product identification the product identification mode can be used to read the manufacturer id and the device id by a software product id entry command in both in-system hardware interface and a/a mux interface modes. the product identification mode is activated by three-bus-cycle command. refer to table 12 for the manufacturer id and device id of A49FL004 and table 14 for the sdp command definition. in fwh mode, the product identification can also be read directly at ffbc0000h for manufacturer id - ?99h? and ffbc0001h for device id in the 4 gbyte system memory map.
A49FL004 preliminary (september, 2005, version 0.0) 17 amic technology, corp. table 12: product identification description address data manufacturer id 00000h 00003h 37h 7fh device id A49FL004 00001h 99h figure 8: system memory map an d device memory map for A49FL004 system memory (top 4m bytes) block 7 (64k bytes) 000000 00ffff 010000 01ffff 020000 02ffff 030000 03ffff 040000 04ffff 050000 05ffff 060000 06ffff 070000 07ffff block 6 (64k bytes) block 5 (64k bytes) block 4 (64k bytes) block 3 (64k bytes) block 2 (64k bytes) block 1 (64k bytes) block 0 (64k bytes) system memory (top 4m bytes) tbl device memory wp for block 6 ~ 0 ffffffffh fff80000h ffc0000h A49FL004 range for additional fw h devices
A49FL004 preliminary (september, 2005, version 0.0) 18 amic technology, corp. table 13: sector/block address table hardware block block size (kbytes) sector sector size (k bytes) sector number address range 127 7f000h - 7ffffh 126 7e000h ? 7efffh 125 7d000h ? 7dfffh 124 7c000h ? 7cfffh 123 7b000h ? 7bfffh 122 7a000h ? 7afffh 121 79000h ? 79fffh 120 78000h ? 78fffh 119 77000h ? 77fffh 118 76000h ? 76fffh 117 75000h ? 75fffh 116 74000h ? 74fffh 115 73000h - 73fffh 114 72000h ? 72fffh 113 71000h ? 71fffh tbl block 7(boot block) 64 16 4 kbytes/sector 112 70000h - 70fffh block 6 64 16 4 kbytes/sector 111 - 96 60000h - 6ffffh block 5 64 16 4 kbytes/sector 95 - 80 50000h - 5ffffh block 4 64 16 4 kbytes/sector 79 - 64 40000h - 4ffffh block 3 64 16 4 kbytes/sector 63 - 48 30000h - 3ffffh block 2 64 16 4 kbytes/sector 47 - 32 20000h - 2ffffh block 1 64 16 4 kbytes/sector 31 -16 10000h - 1ffffh wp block 0 64 16 4 kbytes/sector 15 - 0 00000h - 0ffffh
A49FL004 preliminary (september, 2005, version 0.0) 19 amic technology, corp. table 14: software data protection command definition notes: 1. chip erase is available in a/a mux mode only. 2. address a[15:0] is used for sdp command decoding inter nally and a15 must be ?0? in fwh/lpc and a/a mux modes. ams - a16 = don?t care where ams is t he most-significant address of A49FL004. 3. sa = sector address to be erased. 4. ba = block address to be erased. 5. either one of the product id exit command can be used. 1 st cycle (1) 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle command bus cycles addr (2) data addr data addr data ad dr data addr data addr data block erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba (4) 50h read 1 addr d out sector erase 6 5555h aah 2 aaah 55h 5555h 80h 5555h aah 2aaah 55h sa (3) 30h chip erase (1) 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h byte program 4 5555h aah 2aaah 55h 5555h a0h addr d in product id entry 3 5555h aah 2aaah 55h 5555h 90h product id exit (5) 1 xxxxh f0h product id exit (5) 3 5555h aah 2aaah 55h 5555h f0h
A49FL004 preliminary (september, 2005, version 0.0) 20 amic technology, corp. dc and ac operating range table 15: dc operating characteristics notes: 1. characterized but not 100 tested. table 16: pin impedance (v dd =3.3v, t=25 c, f=1mhz) parameter description test condition max c i/o (1) i/o pin capacitance v i/o = 0v 12pf c in (1) input capacitance v in = 0v 12pf l pin (2) pin inductance 20nh notes: 1. these parameters are characterized but not 100 tested. 2. refer to pci specification. table 17: fwh/lpc interface clock characteristics symbol parameter min max units t cyc clk cycle time 30 ns t high clk high time 11 ns t low clk low time 11 ns clk slew rate (peak-to-peak) 1 4 v/ns init or rst slew rate 50 mv/ns range A49FL004 operating temperature 0 c to +70 c vdd power supply 3.0v ?3.6v limits symbol parameter min typ max units test conditions i cc1 v cc active read current (fwh/lpc) 2 15 ma fwh4 or lframe = v il , f = 33mhz, i out = 0ma, v dd = v dd max i cc2 (2) v cc program/erase current 7 20 ma i sb standby v cc current (fwh/lpc mode) 500 a fwh4 or lframe = v ih , f = 33mhz, v dd = v dd max i ry ready mode v cc current (fwh/lpc mode) 10 ma fwh4 or lframe = v il , f = 33mhz, i out = 0ma, v dd = v dd max i i input leakage current for ic, id[3:0] pins 100 a v in = 0v to v dd , v dd = v dd max i li input leakage current 1 a v in = 0v to v dd , v dd = v dd max i lo output leakage current 1 a v i/o = 0v to v dd , v dd = v dd max v ih input high voltage 0.7v dd v dd +0.5 v v il input low voltage -0.5 0.3v dd v v ol output low voltage 0.1v dd v i ol = 2.0ma, v dd = v dd min v oh output high voltage 0.9v dd v i oh = -100 a, v dd = v dd min
A49FL004 preliminary (september, 2005, version 0.0) 21 amic technology, corp. table 18: fwh/lpc memory read/write operations characteristics symbol parameter min max units t cyc clock cycle time 30 ns t su input set up time 7 ns t h input hold time 0 ns t val clock to data out 2 11 ns t on clock to active time (float to active delay) 2 ns t off clock to inactive time (active to float delay) 28 ns table 19: fwh/lpc interface measurement condition parameters symbol value units v th 4 0.6 v dd v v tl 1 0.2 v dd v v test 0.4 v dd v v max 1 0.4 v dd v input signal edge rate 1v/ns notes: the input test environment is done with 0.1 v dd of overdrive over v ih and v il . timing parameters must be met with no more overdrive that this. v max specifies the maximum peak-to-peak waveform allowed for measuring input timing. production testing may use different voltage values, but must correlate results back to these parameters. figure 9: input timing parameters v tl v th t su v test clk fwh[3:0] or lad[3:0] (valid input data) v max valid inputs t dh
A49FL004 preliminary (september, 2005, version 0.0) 22 amic technology, corp. figure 10: output timing parameters v tl v th t on t off t val v test clk fwh[3:0] or lad[3:0] (valid output data) fwh[3:0] or lad[3:0] (float output data)
A49FL004 preliminary (september, 2005, version 0.0) 23 amic technology, corp. table 20: fwh/lpc interface ac input/output characteristics symbol parameter test conditions min max units 0 < v out 0.3v dd -12 v dd ma 0.3v dd < v out 0.9v dd -17.1(v dd -v out ) ma i oh (ac) switching current high 0.7v dd < v out v dd equation c (1) ma (test point) v out = 0.7v dd -32 v dd v dd > v out 0.6v dd 16v dd ma 0.6v dd > v out > 0.1v dd -17.1(v dd ? v out ) ma i ol (ac) switching current low 0.18v dd > v out > 0 equation d (1) ma (test point) v out =0.18v dd 38v dd i cl low clamp current -3 < v in -1 -25+(v in +1)/0.015 ma i ch high clamp current v dd +4 > v in > v dd +1 25+(v in -v dd -1)/0.015 ma slewr (2) output rise slew rate 0.2v dd -0.6v dd load 1 4 v/ns slewf (2) output fall slew rate 0.6v dd -0.2v dd load 1 4 v/ns notes: 1. see pci specification. 2. pci specification output load is used. table 21: fwh mode interface reset timing parameters, v dd =3.0-3.6v symbol parameter min max units t prst reset active time to v cc stable 1 ms t krst reset active time to clock stable 100 s t rstp reset pulse width 100 ns t rstf reset active to output float delay 50 ns t rst (1) reset inactive time to input active 1 ns note: there will be an 10 s reset latency if a reset procedure is performed duri ng a programming or erase operation. figure 11: reset timing diagram t krst t prst t rst t rstf t rste t rstp program or erase operation aborted v dd clk rst / init fwh[3:0] or lad[3:0] fwh4
A49FL004 preliminary (september, 2005, version 0.0) 24 amic technology, corp. figure 12: a/a mux mode ac input/output reference waveforms v it v ot reference points input output v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic high and v ilt (0.1v dd ) for a logic low. measurement reference points for inputs and outputs are v it (0.5v dd ) and v ot (0.5v dd ). input rise and fall times (10% <-> 90%) are < 5ns note: v it : v input test v ot : v output test v iht : v input high test v ilt : v input low test figure 13: a/a mux mode test load condition cl=30pf to tester to dut
A49FL004 preliminary (september, 2005, version 0.0) 25 amic technology, corp. a/a mux mode ac characteristics table 22: a/a mux mode read operations characteristics symbol parameter min max units t rc read cycle time 270 ns t rst rst high to row address setup time 1 ms t as c r/ address set-up time 45 ns t ah c r/ address hold time 45 ns t aa address to output delay 120 ns t oe oe to output delay 50 ns t df oe output high z 0 30 ns t vcs v dd setup time 50 s t oh output hold from oe or address, whichever occurred first 0 ns table 21: a/a mux write (program/erase) operations characteristics symbol parameter min max units t rst rst high to row address setup time 1 ms t as c r/ address setup time 50 ns t ah c r/ address hold time 50 ns t cwh c r/ to we high time 50 ns t oes oe high setup time 20 ns t oeh oe high hold time 20 ns t wp write pulse width 100 ns t wph we pulse width high 100 ns t ds data setup time 50 ns t dh data hold time 5 ns t bp byte programming time 40 s t ec chip, sector or block erase cycle time 80 ms t vcs v dd setup time 50 s figure 14: a/a mux mode read cycle timing diagram t rst rst address we oe i/o 7 -i/o 0 t rstp row address column address row address column address t rc t as t ah t as t ah v ih t oe t aa t ohz t oh t olz data valid high-z high-z r/c
A49FL004 preliminary (september, 2005, version 0.0) 26 amic technology, corp. figure 15: a/a mux mode write cycle timing diagram t rst rst address o e we i/o 7 -i/o 0 t rstp row a ddress c olumn address t as t a h t as t a h t ds t wp data va lid high-z r/c t oes t wph t d h t oeh t cwh figure 16: a/a mux mode data# polling timing diagram address we oe i/o 7 row address column address high-z r/c write operation complete data in write operation in progress final input command status bit data t oep command input row address column address row address column address row address column address data# data# data status bit figure 17: a/a mux mode toggle bit timing diagram address we oe i/o 6 row address column address high-z r/c write operation complete data in write operation in progress final input command status bit data t oet command input row address column address row address column address row address column address data status bit
A49FL004 preliminary (september, 2005, version 0.0) 27 amic technology, corp. figure 18: a/a mux mode byte program timing diagram address oe we i/o 7 -i/o 0 high-z r/c aa byte program operation in progress t wp byte program command input 55 a0 pd t wph t bp 5555 2aaa 5555 pa pa = byte program address pd = byte program data four-byte byte prog ram command sequence figure 19: a/a mux mode block erase timing diagram address oe we i/o 7 -i/o 0 high-z r/c aa block erase operation in progress t wp block erase command input t wph 5555 2aaa 5555 5555 ba = block address six-byte block erase command sequence 55 80 aa 55 30/50 2aaa ba t be
A49FL004 preliminary (september, 2005, version 0.0) 28 amic technology, corp. figure 20: a/a mux mode chip erase timing diagram address oe we i/o 7 -i/o 0 high-z r/c aa chip erase operation in progress t wp chip erase command input t wph 5555 2aaa 5555 5555 six-byte chip erase command sequence 55 80 aa 55 10 2aaa 5555 t sce figure 21: a/a mux mode product id entry and read timing diagram address oe we i/o 7 -i/o 0 high-z r/c aa t wp t wph 5555 2aaa 5555 three-byte product id entry command sequence 55 90 37 95 7f 0000 0001 0003 t aa t ida figure 22: a/a mux mode product id exit and reset timing diagram address oe we i/o 7 -i/o 0 high-z r/c aa t wp t wph 5555 2aaa 5555 three-byte product id exit and reset command sequence 55 f0
A49FL004 preliminary (september, 2005, version 0.0) 29 amic technology, corp. figure 23: automatic byte program algorithm start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: a0h write command address: pa data: pd i/o 7 = data ? or i/o 6 stop toggle? byte program completed no yes pa: byte program address pd: byte program data
A49FL004 preliminary (september, 2005, version 0.0) 30 amic technology, corp. figure 24: automatic block erase algorithm start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: 80h write command address: 5555h data: aah i/o 7 = data ? or i/o 6 stop toggle? block erase completed no yes ba: block address write command address: 2aaah data: 55h write command address: ba data: 30h or 50h
A49FL004 preliminary (september, 2005, version 0.0) 31 amic technology, corp. figure 25: automatic chip erase algorithm start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: 80h write command address: 5555h data: aah i/o 7 = data ? or i/o 6 stop toggle? chip erase completed no yes write command address: 2aaah data: 55h write command address: 5555h data: 10h
A49FL004 preliminary (september, 2005, version 0.0) 32 amic technology, corp. figure 26: product id command flowchart start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: 90h enter product id mode start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: f0h exit product id mode write command address: xxxxh data: f0h or
A49FL004 preliminary (september, 2005, version 0.0) 33 amic technology, corp. ordering information A49FL004t x - 33 c temperature range c = commercial (0 c to +85 c) clock frequency 33 = 33mhz package type l = plcc x = tsop (8mmx14mm) device number 4 mbit fwh flash memory part no. clock frequency (mhz) boot block location temperature range package type A49FL004tl-33 top 0 c to +85 c 32-pin plcc A49FL004tl-33f top 0 c to +85 c 32-pin pb-free plcc A49FL004tx-33 top 0 c to +85 c 32-pin tsop (8mm x 14 mm) A49FL004tx-33f 33 top 0 c to +85 c 32-pin pb-free tsop (8mm x 14 mm)
A49FL004 preliminary (september, 2005, version 0.0) 34 amic technology, corp. package information plcc 32l outline dimension unit: inches/mm a 1 a 2 a e d y h d d 13 g d b 1 b g e c 5 14 20 21 29 30 32 1 4 e h e l dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.134 - - 3.40 a 1 0.0185 - - 0.47 - - a 2 0.105 0.110 0.115 2.67 2.80 2.93 b 1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.021 0.41 0.46 0.54 c 0.008 0.010 0.014 0.20 0.254 0.35 d 0.547 0.550 0.553 13.89 13.97 14.05 e 0.447 0.450 0.453 11.35 11.43 11.51 e 0.044 0.050 0.056 1.12 1.27 1.42 g d 0.490 0.510 0.530 12.45 12.95 13.46 g e 0.390 0.410 0.430 9.91 10.41 10.92 h d 0.585 0.590 0.595 14.86 14.99 15.11 h e 0.485 0.490 0.495 12.32 12.45 12.57 l 0.075 0.090 0.095 1.91 2.29 2.41 y - - 0.003 - - 0.075 0 - 10 0 - 10 notes: 1. dimensions d and e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only.
A49FL004 preliminary (september, 2005, version 0.0) 35 amic technology, corp. package information tsop 32l type i (8 x 14mm) outline dimensions unit: inches/mm e detail "a" detail "a" b d 1 e d l a a 2 c a 1 pin1 gage plane 0.254 d y dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.0067 0.0087 0.0106 0.17 0.22 0.27 c 0.004 - 0.0083 0.10 - 0.21 e 0.311 0.315 0.319 7.90 8.00 8.10 e - 0.0197 - - 0.50 - d 0.543 0.551 0.559 13.80 14.00 14.20 d 1 0.484 0.488 0.492 12.30 12.40 12.50 l 0.020 0.024 0.028 0.50 0.60 0.70 y 0.000 - 0.003 0.00 - 0.076 0 3 5 0 3 5 notes: 1. dimension e does not include mold flash. 2. dimension d 1 does not include interlead flash. 2. dimension b does not include dambar protrusion.

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